The present invention is directed to semiconductor integrated circuit devices and, more particularly, to the fabrication of semiconductor integrated circuit devices that include isolation trenches.
Various isolation methods have been employed to electrically isolate one or more semiconductor device elements formed in a substrate from other device elements. Such methods have included p-n junction isolation and localized oxidation of silicon (LOCOS). As newer generations of semiconductor device features become increasingly smaller and the number of elements increased, the known methods are often unsuitable or are too difficult to be manufactured in a controllable manner. To isolate such smaller and more highly integrated semiconductor device elements, trench isolation is commonly employed in which a trench is formed in a semiconductor substrate and surrounds the region that is to be electrically isolated and an insulating material is filled in the trench.
To form the isolation trench, one or more etch masking layers are typically deposited on a semiconductor substrate, and then a photoresist film is deposited on the etch masking layer and patterned. Selected regions of the etch masking layer are then removed to expose areas of the semiconductor substrate. The exposed areas of the semiconductor substrate are then etched to a desired depth, and an insulating material is deposited to fill the trench. Any portion of the insulating material that is deposited outside of or above the opening of the trench may then be removed. The etch masking material may then be removed or may be removed prior to the deposition of the insulating material.
As the size of semiconductor device features has further decreased, the width of the isolation trenches has likewise decreased. The depth of the isolation trenches however, has decreased less drastically and, in fact, may increase, such as for vertical transistor DRAMs, so that the ratio of the height of the trench to the width of the trench, known as the aspect ratio, has increased. When an insulating material, such as a high density plasma (HDP) oxide, is deposited in a trench having such higher aspect ratios, voids or seams are often formed within the insulating material located in the trench. The voids may be located entirely below the surface of the semiconductor substrate such that the insulating properties of the isolation trench and the insulating material are degraded. Alternatively, the voids may extend above the surface of the semiconductor substrate so that when the device is subsequently planarized, a seam is opened in the insulating material that may be subsequently filled with a polysilicon film or other conducting material that creates electrical shorts between device elements.
It is therefore desirable to provide a trench isolation process wherein the trench is filled with an insulating material in a manner that prevents the formation of voids and seams.